The present embodiments generally relate to termination circuits for electronic signals, and more particularly, to a passive component minimization of connector pins in a computer system.
In the manufacture of electronic equipment, often there are constraints on real estate or component keep-outs when developing and/or designing a printed circuit board (PCB) for use in the electronic equipment. An exemplary PCB may include a daughterboard for coupling to a motherboard in the computer system. In addition to the daughterboard, such constraints may also occur with other POB""s, for instance control panels (used for power buttons, LED""s, reset buttons, etc. in a computer system).
The daughterboard and other PCB""s are characterized as being very small, and very inexpensive. Such PCB""s are extremely cost-sensitive, and preferably are singled-sided. Accordingly, in the design and development of such PCB""s, the desired characteristics limit a design choice to through-hole, passive components.
However, sometimes for a given design requirement, multiple states need to be transmitted to/from the PCB and pin count on the PCB connectors is limited. Integrated circuits (IC""s) or multiplexers could be used, however they are expensive and complex. Accordingly, such IC""s and/or multiplexers are undesirable, for example from a manufacturing cost standpoint.
Therefore what is needed is an improved passive component minimization of connector pins in a computer system.
In a computer system, a passive component minimization of connector pins configuration includes a motherboard and a daughterboard. The daughterboard includes a selection switch coupled via passive components to a single connector pin, according to a prescribed state of multiple states of the daughterboard. In one embodiment, the passive components include three series connected resistors collectively coupled to the daughterboard connector pin. The motherboard includes a supply voltage and pull-up resistor circuit coupled to a single connector pin, and further includes decoding circuitry coupled to the motherboard connector pin for decoding a voltage level of the motherboard connector pin into binary data. Responsive to a mating of the daughterboard connector pin with the motherboard connector pin, the decoding circuitry converts voltage level data present at the motherboard connector pin into binary data representative of a current state of the daughterboard as a function of the selection switch and passive components of the daughterboard.
A technical advantage is that the present embodiments achieve an improved passive component minimization of connector pins in a computer system.